YORKTOWN HEIGHTS, New York — IBM has unveiled a sub-1 nanometer semiconductor technology based on a three-dimensional transistor design that the company says could extend advanced chip scaling into the angstrom era and support higher performance and energy efficiency for future computing systems.
IBM announced the technology on June 25, describing it as a 0.7-nanometer, or 7-angstrom, node built around a new architecture called “nanostack.” The company said the technology was demonstrated through working semiconductor structures and is intended to address the increasing difficulty of shrinking conventional transistor designs.
The nanostack architecture vertically stacks and staggers nanosheet transistors, allowing more devices to be placed within the same area. IBM said its prototype contains nearly 100 billion transistors on a chip roughly the size of a fingernail, nearly doubling the transistor density of the company’s 2-nanometer technology introduced in 2021.
IBM said technical results indicate the technology could provide up to 50% higher performance or up to 70% greater energy efficiency compared with its 2-nanometer platform. Researchers also demonstrated a 40% scaling improvement in static random-access memory, or SRAM, which IBM said could help address memory requirements associated with advanced artificial-intelligence workloads.
Jay Gambetta, IBM Research director and an IBM Fellow, said the new architecture was designed to move beyond conventional transistor scaling by changing how devices are constructed in three dimensions. IBM said the work was carried out by researchers at its semiconductor research facilities, including the Albany Nanotech Complex in New York.
The development remains a research-stage technology rather than a commercially available manufacturing process. IBM said its work included experimental validation of ultra-thin dielectric bonding, dual-channel engineering and functional CMOS inverter operation. The company also said it was working with semiconductor equipment companies including Lam Research, Tokyo Electron and SCREEN Semiconductor Solutions on processes for future advanced logic manufacturing.
The announcement comes as chipmakers seek new ways to maintain gains in computing performance while managing power consumption and the physical limitations of increasingly small transistor structures. IBM pioneered nanosheet transistor technology used as a foundation for later generations of advanced logic chips.
IBM said it expects the earliest adoption of its nanostack technology at the sub-1-nanometer level could come within about five years, although commercial production would require further development and manufacturing scale-up.
